1. Field of the Invention
The present invention relates to an erasable programmable non-volatile semiconductor memory device.
2. Description of the Related Art
As conventional erasable programmable non-volatile semiconductor memory devices, EEPROMs (electrically erasable programmable read only memories) are known. Of these conventional memory devices, a great deal of attention is especially paid to a NAND-structured cell EEPROM as an EEPROM which can contribute to an increase in packing density. In the NAND-structured cell type EEPROM, a plurality of memory cells are connected in series to constitute a NAND-structured cell block. Each memory cell of the NAND-cell type EEPROM includes an FETMOS structure having a floating gate and a control gate which are insulatively stacked on a semiconductor substrate. A plurality of memory cells are connected in series such that adjacent memory cells share sources and drains, thereby constituting a NAND cell. Such NAND cells are arranged in the form of a matrix to constitute a memory cell array. The drains on one end sides of NAND cells aligned in the column direction of the memory cell array are commonly connected to a bit line through selection gate transistors, while the sources on the other end sides thereof are connected to a common source line through selection gate transistors. The control gates of the memory transistors and the gate electrodes of the selection gate transistors are commonly connected in the row direction of the memory cell array to constitute control gate lines (word lines) and selection gate lines, respectively.
An operation of the NAND cell type EEPROM will be described below.
A data write operation is sequentially performed with respect to memory cells, starting from the memory cell located farthest from a bit line. Assume that the NAND cell type EEPROM has n channels. In this case, a high potential (e.g., 20 V) is applied to the control gate of a selected memory cell, and an intermediate potential (e.g., 10 V) is applied to the control gates of the non-selected memory cells and the gate of the selection gate transistor which are located closer to the bit line than the selected memory cell. In accordance with data, 0 V (for, e.g., "1" data) or an intermediate potential (for, e.g., "0" data) is applied to the bit line. At this time, the potential of the bit line is transferred to the drain of the selected memory cell through the selection gate transistor and the non-selected memory cells.
If there is data to be written ("1" data), a high electric field is applied between the gate and drain of the selected memory cell, and electrons are injected from the substrate into the floating gate. As a result, the threshold value of the selected memory cell is shifted in the positive direction. If there is no data to be written ("0" data), the threshold value is not changed.
In a data erase operation, a high potential is applied to a p-type substrate (an n-type substrate and p-type wells if a well structure is employed), and the control gates of all the memory cells and the gates of the selection gate transistors are set at 0 V. With this operation, electrons are discharged from the floating gates of all the memory cells to the substrate, and the threshold value is shifted in the negative direction.
In a data read operation, a selection gate transistor and non-selected memory cells located closer to the bit line than a selected memory cell are turned on, and 0 V is applied to the gate of the selected memory cell. At this time, "0" data or "1" data is discriminated by detecting a current flowing in the bit line.
In such a conventional NAND cell type EEPROM, a data read or write operation is generally performed with respect to all the bit lines at once. For this reason, in a highly integrated EEPROM, capacitive coupling noise between adjacent bit lines poses problems.
For example, in a 4 M-bit NAND cell type EEPROM, a bit line consisting of an Al film has a line width of 1 .mu.m and a line interval of 1.2 .mu.m. As a result, about 50% (0.25 pF) of the capacitance (about 0.5 pF) of one bit line is the capacitance between adjacent bit lines.
Assume that bit lines are precharged to Vcc=5 V and are subsequently set in a floating state, and data are simultaneously read out to all the bit lines. In this case, if a bit line which is to be kept at 5 V is located between bit lines which are to discharge and change from 5 V to 0 V, the voltage of the bit line which is to be kept at 5 V is decreased to about (1/2) Vcc=2.5 V due to the capacitive coupling. Consequently, no margin is allowed for the voltage of a bit line with respect to a circuit threshold value by which a sense amplifier discriminates "0" data or "1" data, so that this decrease in voltage of a bit line can cause a read operation error.
Similarly, in a data write operation, bit lines connected to memory cells in which no data are written (i.e., "0" data are written) are set at an intermediate potential V.sub.H and are subsequently set in a floating state, while 0 V is applied to bit lines connected to memory cells in which "1" data are written. If, therefore, a non-selected bit line on which no data is to be written is sandwiched between bit lines on which "1" data are to be written, the intermediate potential of the non-selected bit line which is to be kept at the intermediate potential is decreased due to the capacitive coupling. This may cause data write errors in the memory cells connected to the non-selected bit line. Even if write errors are not caused, the threshold value of each memory cell changes, resulting in a deterioration in reliability.
The above-described capacitive coupling noise between bit lines is not limited to NAND cell type EEPROMs but is equally caused in NOR type EEPROMs and in ultraviolet-erasable type EEPROMs. In addition, the problem of noise becomes more serious with an increase in packing density.
As described above, in the conventional EEPROMs, EPROMs, and the like, with an increase in packing density, the capacitive coupling noise between bit lines poses serious problems in terms of characteristics.